1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device with enhanced electrical characteristics.
2. Description of the Related Art
The continuing dimensional shrinkage of semiconductor devices has resulted in increased electrical failures of capacitors, making it difficult to properly operate the semiconductor devices. In particular, in order to form a capacitor, it is necessary to dry-etch a predetermined region of an inter-insulating layer or a conductive layer. In such a case, however, a layer underlying a target layer to be etched may be susceptible to damage, unavoidably degrading electrical characteristics of the capacitor.
For example, in manufacturing a concave type capacitor, a lower electrode and an insulating layer are sequentially formed on a semiconductor substrate, and a predetermined region of the insulating layer is dry-etched to form a capacitor forming region. Then, a dielectric layer and an upper electrode are sequentially formed on the capacitor forming region to fabricate a capacitor. However, the lower electrode disposed below the insulating layer may be over-etched or damaged by O2 plasma during etching.
Also, a planar type capacitor is formed by sequentially forming a lower electrode, a dielectric layer, and a conductive layer on a semiconductor substrate, followed by dry-etching of the conductive layer to form an upper electrode. If the underlying dielectric layer of the upper electrode is entirely etched, a lower electrode material is resputtered. Then, the resputtered flux is attached to a sidewall of the dielectric layer, resulting in leakage current. On the other hand, if the dielectric layer is partially etched, breakdown voltage characteristics vary according to the area of an unetched region. One attempt to solve this problem is to leave the dielectric layer as much as possible even after performing etching, which is achieved by increasing an etching selectivity between the conductive layer and the dielectric layer. In this case, however, an etch rate may be undesirably lowered.